A memory device is required to operate in a high speed and there is a ‘write recovery time’ in a specification representing the performance of the memory device.
The write recovery time tWR presents a time until an auto-precharge operation is performed after data is stored in a unit cell of the memory device. That is, the write recovery time tWR means a minimum time that data is sufficiently stored in an activated bank without being disturbed by an auto-precharge command.
For instance, in a memory device where the write recovery time tWR is synchronously adjusted, when a burst length is set to 2 at a mode register set (MRS) of the memory device and a write operation is performed, the write recovery time tWR becomes a time from a rising edge of a clock where a second data is inputted to a rising edge of a clock where the auto-precharge command is provided. The burst length is the number of data to be sequentially accessed by one command.
When developing the memory device, as methods for adjusting the write recovery time tWR, there are a synchronous method for performing the auto-precharge operation according to a certain number of operational clocks after the write operation is performed and an internal burst length period is passed, an asynchronous method for executing the auto-precharge operation according to a fixed delay time after the write operation is performed and the internal burst length period is passed, and a compounded method adopting both of the synchronous and the asynchronous methods.
One of the above methods is appropriately selected according to the usage and an operational frequency of the memory device, and the variation of PVT (process, voltage, temperature).
In case that there are lots of manufacturing variation at the beginning of developing a memory device, the write recovery time tWR is adjusted by using the synchronous method. On the other hand, when using a wide operational frequency bandwidth, it is preferable to adjust the write recovery time tWR by using the asynchronous method.
FIG. 1 is a block diagram of a conventional memory device.
Referring to FIG. 1, the conventional memory device includes a write recovery time controlling block 10 for receiving an auto-precharge control signal apcgpz and delaying the received signal apcgpz as long as a certain time corresponding to a write recovery time, an auto-precharge operation controlling block 20 which outputs an auto-precharge execution signal apcg after receiving the auto-precharge control signal apcgpz in response to a read signal Read when an operation corresponding to a read command is in progress and outputs the auto-precharge execution signal apcg by receiving the auto-precharge control signal apcgpz in response to a write signal Write when an operation corresponding to a write command is in progress, and a memory core 30 which contains a plurality of unit cells, wherein data stored in a selected unit cell is accessed in response to the read/write command, and performs the auto-precharge operation in response to the auto-precharge execution signal apcg outputted from the auto-precharge operation controlling block 20.
Hereinafter, the operation of the conventional memory device is explained in detail with reference to FIG. 1.
At first, the auto-precharge operation controlling block 20 outputs the auto-precharge execution signal apcg by receiving the auto-precharge control signal apcgpz responding to the read signal Read when the operation corresponding to the read command is in progress. The read signal Read is generated by decoding a command, which is inputted to perform the read operation, at a command decoder (not shown). The auto-precharge control signal apcgpz is internally produced to perform the auto-precharge operation that is executed after the memory device accesses data in response to one command.
Meanwhile, the auto-precharge operation controlling block 20 outputs the auto-precharge execution signal apcg by receiving a signal outputted from the write recovery time controlling block 10 responding to the write signal Write when the operation corresponding to the write command is in progress. Herein, the write signal Write is generated by decoding a command, which is inputted to perform the write operation, at the command decoder.
The write recovery time controlling block 10 delays the auto-precharge control signal apcgpz inputted thereto as long as a certain time and outputs a delayed signal to the auto-precharge operation controlling block 20.
If the auto-precharge execution signal apcg is enabled and provided thereto, the memory core 30 performs the auto-precharge operation in response to the enabled auto-precharge execution signal apcg.
The reason why generating the auto-precharge execution signal apcg by using the signal outputted from the write recovery time controlling block 10 during the write operation is that the write recovery time tWR should be secured during the write operation as afore-mentioned. The write recovery time tWR represents a time until performing the auto-precharge operation after accessing data in response to the write command.
The write recovery time controlling block 10 uses a synchronous method or an asynchronous method so as to receive the auto-precharge control signal apcgpz, delay it and output a delayed signal, to thereby secure the write recovery time tWR.
If the write recovery time controlling block 10 uses the synchronous method, it performs the write operation by receiving a clock signal clk and delays the auto-precharge control signal apcgpz as long as a time corresponding to the fixed number of clocks after a period corresponding to the burst length BL is passed, thereby outputting the delayed precharge control signal.
On the other hand, if the write recovery time controlling block 10 adopts the asynchronous method, it delays the auto-precharge control signal apcgpz as long as a certain time after the period corresponding to the burst length BL is passed, and outputs the delayed precharge control signal.
In general, in the early stage of the development of the memory device, the synchronous method is used because there is the great variation in a manufacturing environment. On the other hand, in case that the variation of the manufacturing environment becomes stable, the asynchronous method is utilized since a frequency of the operational clock can be widely used.
However, in order to design a flexible device having various uses as afore-mentioned, there is a problem of increasing the development time and cost of the device according to the application.